1. Field
Example embodiments are directed to a method of fabricating semiconductor devices, for example, a method of fabricating semiconductor devices having a gate silicide.
2. Description of Related Art
In semiconductor devices, discrete devices, for example, MOS transistors, may be used as switching devices. As integration densities of semiconductor devices increase, the MOS transistors may be gradually scaled down. As a result, channel lengths of the MOS transistors may be shortened, and short channel effects may occur. The shortening of the channel lengths may result in a more narrow width of gate electrodes. Accordingly, electrical resistance of the gate electrodes may increase, and gate capacitance C as well as the resistance R of the gate electrodes may increase. Transmission speed of electrical signals applied to the gate electrodes may become slower due to an increased resistance-capacitance (RC) delay time.
A method of reducing an electrical resistance of a gate electrode may be applied to reduce this effect. For example, a polysilicon layer pattern and a titanium nitride layer pattern may be formed on a semiconductor substrate, and a gate spacer may be formed on the sidewalls of the polysilicon layer pattern and the titanium nitride layer pattern. The polysilicon layer pattern and the titanium nitride layer pattern may be formed sequentially, for example. A titanium layer may be formed on the semiconductor substrate including the gate spacer, and rapid thermal annealing may be performed to form a source/drain silicide including titanium silicide. The titanium nitride layer pattern may function as a silicide barrier layer to reduce or prevent silicide from being formed by the reaction of the polysilicon layer pattern and the titanium layer. The unreacted titanium layer and the titanium nitride layer pattern may be removed. A cobalt layer may be deposited and annealed to form a gate silicide including cobalt silicide. The titanium nitride layer pattern may not be completely removed because of a large diameter of a semiconductor wafer used when fabricating a semiconductor device with a narrow critical dimension gate electrode. When gate silicide is formed with the titanium nitride layer pattern not being completely removed, the remaining titanium nitride layer pattern may obstruct the gate silicide formation, which may lead to deterioration of electrical characteristics of the gate electrode.